1. Field of the Invention
The present invention relates to a liquid crystal display device, and a timing controller and a signal processing method to be used in the liquid crystal display device and more particularly to the liquid crystal display device capable of simultaneously achieving reduction of noises, miniaturization and thinning of a signal processing board, and high-speed transmission of image data, and to the timing controller and the signal processing method to be used in the liquid crystal display device.
2. Description of the Related Art
In a liquid crystal display device, EMI (ElectroMagnetic Interference) noises occur in some cases. The reasons for the EMI noises are as follows:    (1) As the liquid crystal display device becomes larger in size and higher definition, an amount of image data to be transmitted to its display panel becomes enormous and the transmission of image data must be further sped up.    (2) As a moving image improving technology, a frequency having a refresh rate of 60 Hz or more is used, which causes the higher-speed transmission of image data.    (3) As components other than a display region of a display panel becomes smaller in size and thinner, a signal processing board for transmission of image data is also miniaturized and is made thinner.
Due to requests for the high-speed transmission of image data, a high-frequency component is emitted as the EMI noise from a wiring for the transmission of data signals and clock signals. Moreover, due to an insufficient area for a reference potential wiring (ground) caused by the miniaturization and thinning of a signal processing board, the EMI noises are also emitted from the reference potential wiring. Therefore, the advent of the liquid crystal display device is expected which can achieve the suppression of EMI noises and simultaneously the miniaturization and thinning of the signal processing board even when image data is to be transmitted at higher speed.
To solve this problem, a method of driving a liquid crystal display device is disclosed as the related art in Japanese Patent Application Laid-open No. 2006-267313 (Patent Reference 1). In this driving method, as shown in FIG. 12A, a frequency of an internal clock (Internal CLK) to be inputted to a source driver is set to be different from a frequency of an input clock (Input CLK) inputted from a system device during an invalid period and, therefore, a peak voltage level of a noise (GND noise) being superimposed on a reference potential wiring formed on a data side substrate having a source driver. Owing to this, the EMI noises caused by GND noises emitted from the liquid crystal display device are decreased. Also, in the case where signals from a timing controller are outputted through two ports, as shown in FIG. 12B, internal clocks (internal CLK1 and internal CLK 2) are out of phase with each other to avoid synchronization (in phase), whereby an influence by noises on the reference potential wiring can be reduced. By these method, the occurrence of peaks of noises from the reference potential wiring is reduced, thus decreasing the EMI noises.
Another attempt for the reduction of noises in a liquid crystal display device is disclosed in Japanese Patent Application Laid-open No. Heil0-207434 (Patent Reference 2). In the disclosed liquid crystal display device, signals from a timing controller are outputted through N ports and, as shown in FIG. 13A, in response to an input clock signal fHz, internal clocks from each output port are frequency-divided into a clock signal f/N, whereby EMI noises caused by a high-frequency component can be suppressed.
However, the above conventional technologies have the following problems. That is, in the liquid crystal display device disclosed in the Patent Reference 1, in the case shown in FIG. 12A, it is true that noises in the reference potential wiring during an invalid period are reduced, however, noises during the transmission of internal data signals are not decreased. Also, in the case shown in FIG. 12B, the peak noises in the reference potential wiring are reduced, however, periodic potential changes in the reference potential wiring still remain and no decrease in the influence by noises occurs.
The liquid crystal display device disclosed in the Patent Reference 2 has a problem in that, since the internal clock signals are frequency-divided into f/N, as shown in FIG. 13B, noises occur in the reference potential wiring. In this case, a display region of a display panel is divided in a manner to be equal in area, the frequencies of the internal clock signals from each output port of the timing controller are set to be equal. As a result, superimposition of phases of signals having the same frequency occurs, which causes a larger noise peak and the above problems remain unsolved.